//DMX反馈 DMX协议解码模块 jzhang	140814
//201712-0	邵重写
module	dmx_none_space_rx	(
			input	wire		sclk,
			input	wire		resetb,
			
			input	wire		t_us,
			input	wire		dmx_rec_reset,
			
			input	wire	[7:0]	dmx_ack_in,
			input	wire	[2:0]	active_port,	
			
			input	wire	[9:0]	div_count_max,
			
			output	reg		dmx_sync,
			output	reg	[7:0]	dmx_data,
			
			output	wire	[31:0]	tout	
			);
	
reg	[2:0]	state;
reg	[2:0]	t_us_r;
reg	[7:0]	din_r,din_local;
reg		active_data;
reg		dmx_neg_flag,dmx_pos_flag,active_data_r;
wire		dmx_space_max,dmx_mab_max;
reg	[9:0]	slot_base_cnt;
reg	[4:0]	slot_cnt;
reg		bit_clk,bit_clk_r;
reg		data_sync;
reg	[7:0]	dout;
reg	[9:0]	bit_rate;

parameter	IDLE	=3'b001;
parameter	SLOT	=3'b010;
parameter	STOP	=3'b100;

assign	tout = {dmx_data,dmx_sync,bit_clk_r,bit_clk,active_data};
//******************************************************************/
//			   ����125m �� ����ʱ�ӵķ�Ƶ���� div_count_max*5/12
//******************************************************************/
wire	[15:0]	div_count_a;
wire	[12:0]	div_count_multi_5;
reg	[15:0]	t1;
reg	[9:0]	t1_cnt;

mult_16_16  div_count(
	.dataa({6'h0,div_count_max[9:0]}), 
	.datab(16'h5), 	
	.result(div_count_a));

assign	div_count_multi_5=div_count_a[12:0];

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		t1<=0;
	else if(t1[15]==1 || t1==0)
		t1<=div_count_multi_5;
	else
		t1<=t1-12;

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		t1_cnt<=0;
	else if(t1[15]==1 || t1==0)
		t1_cnt<=0;
	else
		t1_cnt<=t1_cnt+1;

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		bit_rate<=0;
	else if(t1[15]==1 || t1==0)
		bit_rate<=t1_cnt-1;
		
always @(posedge sclk or negedge resetb)
	if(resetb==0)
	begin
		t_us_r	<=0;
		din_r	<=0;
		din_local<=0;
	end
	else 
	begin
		t_us_r	<={t_us_r[1:0],t_us};
		
		din_r		<=dmx_ack_in;
		din_local	<=din_r;
		
	end

//***************选择被检测信号并滤波*********************
reg		ddd, ddd_t;
reg	[7:0]	active_count;

//信号选择
always @(posedge sclk or negedge resetb)
	if(resetb==0)
		ddd<=0;
	else
	case(active_port)
		0:	ddd<=din_local[0];
		1:	ddd<=din_local[1];
		2:	ddd<=din_local[2];
		3:	ddd<=din_local[3];
		4:	ddd<=din_local[4];
		5:	ddd<=din_local[5];
		6:	ddd<=din_local[6];
		7:	ddd<=din_local[7];
		default:ddd<=din_local[0];
	endcase

//被检测信号锁存
always @(posedge sclk)
	ddd_t <= ddd;

//信号保持计数
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		active_count <=	0;
	else if (ddd != ddd_t)
		active_count <= 0;
	else if (active_count[7] == 0)
		active_count <= active_count + 1;

//信号滤波：50*8ns=400ns
always @(posedge sclk or negedge resetb)
	if (resetb == 0)
		active_data <= 0;
	else if (active_count > 49)
		active_data <= ddd_t;

//***************串口信号分析*********************
always @(posedge sclk or negedge resetb)
	if(resetb==0)
		state<=IDLE;
	else if(dmx_rec_reset==1)
		state<=IDLE;
	else
		case(state)
			IDLE:	
				if(dmx_neg_flag==1)
					state<=SLOT;
			SLOT:	
				if(slot_cnt==10 && data_sync==1)
				begin
					if(active_data==1)
						state<=STOP;
					else
						state<=IDLE;
				end
			STOP:
				if(dmx_neg_flag==1)
					state<=SLOT;
				else
					state<=STOP;
					
			default:state<=IDLE;
		endcase

always @(posedge sclk)
		active_data_r<=active_data;

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		dmx_neg_flag<=0;
	else if(active_data_r==1 && active_data==0)
		dmx_neg_flag<=1;
	else
		dmx_neg_flag<=0;

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		dmx_pos_flag<=0;
	else if(active_data_r==0 && active_data==1)
		dmx_pos_flag<=1;
	else
		dmx_pos_flag<=0;			

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		slot_base_cnt<=0;
	else if(state!=SLOT)
		slot_base_cnt<=0;
	else if(slot_base_cnt==bit_rate)
		slot_base_cnt<=0;
	else
		slot_base_cnt<=slot_base_cnt+1;


always @(posedge sclk or negedge resetb)
	if(resetb==0)
		bit_clk<=0;
	else if(state!=SLOT)
		bit_clk<=0;
	else if(slot_base_cnt==bit_rate)
		bit_clk<=~bit_clk;

always @(posedge sclk)
	bit_clk_r<=bit_clk;

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		slot_cnt<=0;
	else if(state!=SLOT)
		slot_cnt<=0;
	else if(bit_clk_r==0 && bit_clk==1)
		slot_cnt<=slot_cnt+1;


always @(posedge sclk or negedge resetb)
	if(resetb==0)
		data_sync<=0;
	else if(bit_clk_r==0 && bit_clk==1)
		data_sync<=1;
	else
		data_sync<=0;
		

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		dout<=0;
	else if(state!=SLOT)
		dout<=0;
	else if(bit_clk_r==0 && bit_clk==1)
		dout<={active_data,dout[7:1]};

//always @(posedge sclk or negedge resetb)
//	if(resetb==0)
//		dmx_sync<=0;
//	else if(data_sync==1 && slot_cnt==9)
//		dmx_sync<=1;
//	else
//		dmx_sync<=0;

//������Ч����д��BUF
always @(posedge sclk or negedge resetb)
	if(resetb==0)
		dmx_sync<=0;
	else if(data_sync==1 && slot_cnt==10 && active_data==1)
		dmx_sync<=1;
	else
		dmx_sync<=0;
		

always @(posedge sclk or negedge resetb)
	if(resetb==0)
		dmx_data<=0;
	else if(data_sync==1 && slot_cnt==9)
		dmx_data<=dout;

endmodule